Non-volatile memory cells are well known in the art. One prior art non-volatile memory cell 10 is shown in FIG. 1. The memory cell 10 comprises a semiconductor substrate 12 of a first conductivity type, such as P type. The substrate 12 has a surface on which there is formed a first region 14 (also known as the source line SL) of a second conductivity type, such as N type. A second region 16 (also known as the drain line) also of N type is formed on the surface of the substrate 12. Between the first region 14 and the second region 16 is a channel region 18. A bit line (BL) 20 is connected to the second region 16. A word line (WL) 22 (also referred to as the select gate or row line) is positioned above a first portion of the channel region 18 and is insulated therefrom. The word line 22 has little or no overlap with the second region 16. A floating gate (FG) 24 is over another portion of the channel region 18. The floating gate 24 is insulated therefrom, and is adjacent to the word line 22. The floating gate 24 is also adjacent to the first region 14. A coupling gate (CG) 26 (also known as control gate) is over the floating gate 24 and is insulated therefrom. An erase gate (EG) 28 is over the first region 14 and is adjacent to the floating gate 24 and the coupling gate 26 and is insulated therefrom. The erase gate 28 is also insulated from the first region 14. The cell 10 is more particularly described in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program is as following. The cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 28 with the other terminals equal to zero volts. Electrons tunnels from the floating gate 24 into the erase gate 28 causing the floating gate 24 to be positively charged, turning on the cell 10 in a read operation, the resulting memory cell erased state is known as ‘1’ state. The cell 10 is programmed, through source side hot electron programming mechanism, by applying a high voltage on the coupling gate 26, a high voltage on the source line 14, a medium voltage on the erase gate 28, and a programming current on the bit line 20. A portion of electrons flowing across the gap between the word line 22 and the floating gate 24 acquire enough energy to inject into the floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 10 in a read operation, the resulting memory cell programmed state is known as ‘0’ state. The cell 10 in the same row is inhibited in the programming by applying an inhibit voltage on its bit line 20.
The conventional array architecture is illustrated in FIG. 2. The array includes non-volatile memory cells 10 of the type shown in FIG. 1, arranged in a plurality of rows and columns in the semiconductor substrate 12. Adjacent to the array of non-volatile memory cells are address decoders (e.g. XDEC 40, YMUX 42, HVDEC 44) and a bit line controller (BLINHCTL 46) used to decode addresses and supply the various voltages to the source 14, drain and bit line 16/20, WL 22, FG 24, CG 26 and EG 28 during read, program, and erase operations for selected memory cells.
Erase and program operations require a relatively high voltage, which is supplied by a charge pump CHRGPMP 48. Typically, an entire word of data (e.g. 37 bits that include 32 bits of data and 5 bits of ECC) is written during a single program operation into a single row of memory cells. Therefore, a typical configuration for the array is that there are 4096 columns of memory cells, which provides enough memory cells in each row to store an entire word of data. FIG. 3 illustrates the electrical configuration of the various rows and columns. In the example shown, the array is broken down into sectors, with each sector including 8 rows (i.e. rows 0-7). In operation, a row with its selected memory cells is programmed in one programming operation. To accomplish this, the word lines (WL), the coupling gate lines CG and the erase gate lines EG extend all the way across each row, and electrically connect to each memory cell in the row. This means that during a program operation, the charge pump 48 must be capable of supplying the high voltages to the entire row of selected memory cells. The same is true for erase operations. One consequence is that such a charge pump having the capability of supplying the high voltage across the entire row of selected memory cells is relatively large in size and thus consumes a significant amount of space on the chip. Another consequence is the amount of power consumed by the charge pump.
There is a need for a memory cell design and operation thereof that would allow the reduction of the charge pump size and power consumption.